Erik R. Hosler, FylEx
Introduction
The economy of scale is essential for both science and industry. Quarks, gluons, and the Higgs boson (to name a few) would all have gone undiscovered without the economy of scientific scale, where particle accelerators are essential to access the energies at which these fundamental particles can be observed. The accelerator community has pushed the frontier of scientific discovery for decades with innovation to build more powerful and capable machines. From particle “smashing” accelerators to accelerator-driven free-electron lasers[1-3], each machine generation has necessarily improved the cost, footprint, and manageable beam current per GeV of acceleration, driving the economy of scale and further proliferating accelerator applications and avenues of scientific investigation [4-6].
Similarly, our modern society would not exist without semiconductor “gigafactories” [7]. Moore’s Law is predicated on the idea that creating more transistors per square area will lower the intrinsic, per unit manufacturing costs, and while the cost of building a semiconductor factory doubles every four years (Rock’s Law) [8], rising to north of $20B today [9]. Nevertheless, Moore’s Law is most certainly alive, and thriving, in the age of Artificial Intelligence (AI) [10-12]. However, just like data center scaling in support of inference engines [13-15], the environmental toll of ultrascale integration (even in conjunction with advanced packaging strategies) semiconductor manufacturing has become staggering [16]. Taiwan Semiconductor Manufacturing Company (TSMC) currently consumes more than 9% of Taiwain’s entire electrical capacity and will need an additional 2% in the coming years, amounting to 60% of the planned national capacity [17]. This equates to three nuclear reactors worth of electricity [18-20]. At the center of this massive electrical consumption is a singular manufacturing tool, the extreme-ultraviolet (EUV) photolithography scanner.
Light is a critical enabler for leading-edge semiconductor manufacturing. The properties, quality, and quantity of lithographic light determine the manufacturable device performance and economics, and have been the backbone of Moore’s law economics [21-24]. By extension, innovations in light source technology have enabled tectonic shifts and consolidation in the semiconductor industry, where the use of EUV lithography is a dividing chasm between advanced and legacy technologies. For example, sub-7nm nodes, which require EUV lithography to be economically viable, are 59% of TSMC’s earnings but <400k out of an installed ≃15M 300mm equivalent wafer start capacity [25, 26]. With both the highest investment and profitability skewed toward leading-edge technologies, and the subsequent consolidation of skilled labor around those at the forefront of its development and execution, the competitive landscape disproportionately favors the leaders. These skewed economies of scale divide not only technologies but also the commercial marketplace and, by extension, national economies. Recent worldwide legislation has striven to break down the centralization of advanced semiconductor manufacturing in the face of these economic hurdles [27], however, this expansion of domestic capability-enabling capacity will only exacerbate the overall carbon footprint and environmental challenge of the industry [28]. While light is the enabler for advanced semiconductor manufacturing, it has also become an essential triad for technology leadership, security, and economics.
EUV scanners, built by ASML, are the most advanced lithography tools in the world. Utilizing 13.5nm light, generated by a tin laser-produced plasma (LPP), features as small as a few nanometers can be printed with angstrom precision [29, 30]. Advances in sources, optics and mechatronics allow each new lithography tool generation to print smaller features at higher precision (overlay and edge-placement error reduction) [31] thereby establishing the transistor technology ground rules, i.e. what is the most advanced chip a fabless (e.g., Nvidia, AMD, Microsoft, Mediatek, Qualcomm, etc...) or integrated electronic device manufacture (e.g., Intel, Samsung) can manufacture [32]. Here, there is a distinct difference between a demonstrable process technology and a manufacturable one. While there are certainly many novel proposals and demonstrations of both unique device architectures pushing the boundaries of electronics [33, 34], the ability to produce trillions of devices per 300mm wafer with yields targeting 90% or better requires substantial process engineering and an in-depth knowledge and control of semiconductor capital equipment [35, 36].
EUV lithography has several distinct differences compared to prior lithography technologies, specifically when it comes to the photochemical mechanisms and the interplay between light source power scaling and optical column transmission impact the cost efficiency of the patterning process [37-40]. As target feature size and desirable pattern roughness decreases, the necessary photoresist dose (i.e., the energy required to resolve the target feature) increases, which implies that the number of incident EUV photons per unit area must proportionately increase to maintain the EUV scanner productivity (i.e., processed wafers per hour). EUV’s financial viability is therefore strongly tied to source power, which has drawn the industry to constantly be looking for ways to increase the deliverable photon flux on wafer [41].
Evolution of Accelerators and EUV Lithography
Free-electron lasers and EUV lithography both have their origins in the 80’s and 90’s [42-46]. In the subsequent decades of mutual maturation, an interwoven history of advocation and speculation has existed concerning whether the two technologies would become mutually supportive and enabling. Shortly after the creation of the EUV-LLC [47, 48], when the choice of EUV light source was far from clear, FELs were proposed as a potential light source capable of generating kWs of extreme-ultraviolet light in support of lithography [49, 50]. There have been multiple design iterations as accelerator and FEL technology advanced, but regardless of configuration, the requirement of multiplexing a single light source to multiple end-stations (lithography tools) persisted as a result of cost and scale [51-55]. While compact versions were proposed, insufficient progress was made toward viability, and moreover, the designs were insufficiently compact [56-60]. Fab’s require that each tool in the cleanroom maintain its support equipment in the subfab within the same footprint as occupied in the ballroom. This allows for optimal tool compaction and modularity in layout. While EUV lithography has become a necessary exception, space remains at a premium both in and around a cleanroom [61], and given the risk averse attitude to paradigm shifts in the semiconductor industry [62, 63], adoption of the ”multi-user” light source facility (e.g., synchrotron or FEL) was viewed as a non-starter.
A critical inflection point occurred in 2013 with prognostication of the 7nm technology node heralding the demise of Moore’s Law. The patterning requirements at 7nm necessitated either costly 193 nm immersion lithography multipatterning or EUV lithography, which was delayed primarily because of the EUV light source [64-66]. As semiconductor manufacturers expressed concerns over the source power roadmap [50], concerted analysis began within the industry to evaluate the state-of-the-art of accelerator and FEL technology as a viable lithography light source [67]. Multiple study programs were launched, most notably by ASML [68], a consortium of US National Labs and RadiaBeam, KEK [69], and GLOBALFOUNDRIES [70]. Although there were variations in the final design recommendations between the various programs, common threads emerged. The economy of scale for an accelerated-based lithography sector would indeed necessitate simultaneous multiplexing across multiple end-stations (lithography tools). Specifically, efficient creation and distribution of multiple, independent photon beams would be essential. Moreover, the ability of the light source to provide light to each end-station at near 100% availability was critical but highly suspect. For context, a semiconductor fab producing 100k 3nm wafers a month generates up to $3M per hour in revenue.
Several solutions emerged to resolve both the distribution and availability concerns. For an electron accelerator driving a free-electron laser, either the electron or the photon beam could be divided to service multiple end-stations and were publicly proposed by GLOBALFOUNDRIES [71-73]. Electron multiplexing had long been enabled at the Jefferson Accelerator Facility CEBAF machine [74], and photon beam splitting at free-electron lasers had recently been demonstrated at FLASH and LCLS [75-78]. To resolve concerns regarding availability, redundancy was proposed to first order, where two accelerators housed in separate radiation vaults would allow safe maintenance in operation of the overall complex [79, 70]. Furthermore, the exact configuration of the accelerator in conjunction with the maturity of the constituent hardware was highlighted as essential for industrial operations [73].
Figure 1: Illustrative layout of a lithography sector in the semiconductor fab cleanroom. Gray is lithography scanner, blue is process track, orange and pink are various metrology and inspection tools, black are mask and wafer storage, gold is overhead transport of wafers in either red or green pods.
Lastly, while it is common place for particle accelerators to be the center point of scientific user facilities, the equipment paradigm in semiconductor manufacturing focuses on independent, self-contained, unit scalable hardware. Industrial engineering relies on this modularity for scale and operational efficiency (e.g., flexible routing between matched tools, avoiding single-point congestion, product staging, etc...). Moreover, the economy of scale relies on phased capacity construction. This allows for technology process research and development to be conducted on the exact (or very similar) tools as will be used for volume production simply by increasing the number of tool copies. Prior to 2019, it was an annually revisited open question within the semiconductor industry as to whether EUV lithography was ready for high-volume manufacturing (HVM), or if it ever would be, tracked by a scorecard at the International Symposium on EUV Lithography. In light of this existential question, in conjunction with the industrial engineering requirement of “copy exact” between R&D and HVM equipment, the idea of building a large scale light source facility to solve one of several outstanding critical issues faced by the industry (defectivity impacting device yield was another challenge) [80, 81] was deemed too high risk.
In 2019, TSMC announced the introduction of EUV process into HVM through their N7+ technology node [82], and ever since it has been a race within the industry to install the most EUV lithography scanners and operate them most efficiently/effectively to drive time-to-market and product yield. It was no longer a question of ‘if’ EUV lithography would be used but how much could the technology be leveraged to drive transistor density and performance, opening a new avenue for the economy of scale within Moore’s Law. Now, in 2024, EUV sustainability is challenged [83] by the megawatts of electrical power, hundreds of liters of hydrogen per minute, and thousands of gallons of water required for each high-end lithography scanner [84, 18]. Irrespective of the sustainability challenges, the industry must also expand EUV lithography capability by increasing the numerical aperture [85, 83], improving depth of focus [86], minimize stochastic effects [87], increasing source power [29], improve overlay performance, minimize k1 [88], and ensure toolset flexibility [89].
FEL Industrialization and Photolithography
The semiconductor industry will strive to resolve the future lithography challenges utilizing the proven LPP architecture, however, there is renewed interest in developing FEL sources for lithography now that EUV is entrenched as the driving force of leading-edge manufacturing. Evaluating the future EUV lithography challenges reveals advantages for a utility scale FEL light source, and has sparked the formation of several start-up companies and activity from established contributors.[90, 16, 91, 53, 54] Moreover, state-of-the-art innovations in high-repetition rate, superconducting accelerator-based FELs (e.g., LCLS-II [92, 93] and XFEL [94]) highlight the maturity of critical components and infrastructure necessary for an industrial-class accelerator facility [95]. Recent discussions within the FEL community have further highlighted the lack of technology showstoppers as well as strong confidence in the established component hardware (cryomodules, accelerator cavities, cryogenic plants, undulator magnets, conventional steering magnets, ultrafast lasers, solid-state RF amplifiers, etc...) [19].
Critical to the success of an industrial FEL program is a parameter optimization prioritizing robust operations. Focusing on system and sub-system uptime as well as stability of a limited number of desired output parameters is far less complex than most accelerator projects to-date. Unlike a scientific user facility, where capability and flexibility are required by design, an industrial light source can be engineered, even over-engineered, for a few applications or even a singular use case [96]. When compared to previously constructed accelerator facilities, an EUV FEL for lithography is more akin to the IR Demo than LCLS-(I/II/HE) [97, 92, 93]. As single purpose program originally, the IR Demo was designed to efficiently and decisively ’illuminate’ adversarial targets - to invent and prevent surprise [98-102]. With its fixed initial objective, the IR Demo was designed, green field built, and achieved its first power on target within three years, comparable to required industrial timelines. Comparatively, 10-20 years are typically required to plan and build a scientific user facility (e.g., LCLS was 11-years from design study[103] to ”first light”[104] and reused substantial existing infrastructure). Moreover, the IR-Demo is the only FEL to demonstrate 10’s of kilowatt-class performance and single operator start-up and operation, both of which are in-line with industry expectations.
Combining the engineering and operation modalities of the IR Demo with the maturation of accelerator components and technologies driven by FELs and accelerators over the past 25-years, an industrial FEL for the semiconductor industry can now be built with the necessary performance specifications [71]. In so doing, an accelerator-based industrial light source will become utility-scale infrastructure similar to water, gas, heat/exhaust, and electricity. Such a paradigm shift will reshape how light is both utilized and deployed in the fab, a shift which must be justified by the benefits. Projections indicate a reduction in EUV exposure cost approaching an order of magnitude with a similar reduction in the overall carbon footprint [16]. However, similar to other industrialized accelerator applications [105-108], FELs will need rigorous, fixed-purpose design, a robust supply chain of critical components, a trained workforce, and most importantly, a financially viable market. With the semiconductor industry as the market driver, and lithography as the targeted application, the critical components and workforce skills can be derived [70, 73]. Most critical will be the FEL cost and availability, as these will directly impact the heart of semiconductor economics. Beyond the semiconductor industry, there are numerous other potential drivers for industrialization, however, none of which has a comparable combination of need/benefit (both to the industry and society) and profitability.
FEL industrialization for semiconductor manufacturing will be a renaissance for the scientific community. With scale, comes dramatic reductions in costs throughout the supply ecosystem for accelerator components as a result of guaranteed demand. Should FELs be adopted for lithography applications, construction of five or more GeV-class accelerators will be built, per year. Establishment of a robust market will allow component suppliers and support infrastructure companies to reliably and permanently scale their facilities and capabilities. Moreover, the insatiable desire of the semiconductor industry for innovation (i.e., Moore’s Law) will continuously feed R&D in accelerator and FEL physics/engineering, similarly as it has many other fields (e.g., Semiconductor Research Corporation). This feedback between industry and the scientific community will lower the cost of major scientific user facility construction/operation as well as encourage student enrollment and study in STEM fields, fueling future scientific endeavors.
Figure 2: Diagram of an industrialized FEL light source utility for a semiconductor fab, incorporating redundancy and multi-application support leveraging the advantages in power scalability, light parameter selection, and wavelength tunability. All numerical aperture variations of EUV lithography can be driven at 13.5nm or shorter wavelengths while simultaneously powering metrology and inspection applications from 70-2nm.
Light source innovations have propelled Moore’s Law throughout the decades, with technology advances in lithography filtering through to other light-based fab operations (e.g., metrology and inspection). Introduction of a utility scale, accelerator light source promises to be the last light source innovation the industry will require given its intrinsic extensibility. Fab operations with an onsite FEL ensure availability of any wavelength or light parameter required with minimal carbon footprint and maximum reuse of technology. Furthermore, the expansion of metrology and inspection applications beyond capabilities of existing bulb, laser, or plasma light source provide an opportunity to expedite cycles of learning for both R&D as well as volume production/yield ramp. However, it is only with both the economy of scale of the semiconductor fab and industry as well as the scientific economy of scale within the accelerator and FEL communities that both can be overwhelmingly productive. Where historically light source technology has been an innovation stumbling block for the industry, accelerators will usher in an era of light-enabled innovation, expanding the transistor design space, and ensuring the longevity of Moore’s Law for the next twenty-five years.
Acknowledgments
I am indebted to Professor William Barletta, Harry Levinson, Moshe Preil, and Obert Wood for their insight and support to pursue accelerator physics for semiconductor applications. In addition, I am grateful to all those I have collaborated with throughout the last decade on FEL-based light source design considerations across the technical and leadership staffs at the US National Labs, worldwide accelerator facilities, and component manufacturers.
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